Introduction
In the context of the rapidly growing semiconductor industry, the demand for compact, high-performance, and energy-efficient devices is constantly increasing. This has driven the emergence of advanced chip packaging technologies, among which WLCSP (Wafer-Level Chip Scale Package) stands out. This technology allows chips to be packaged directly on the wafer, instead of separating each die as in traditional methods. This article delves into the “Process Flow of WLCSP: From Wafer to Finished Package”, helping you understand how this technology works, the value it brings, and why it is becoming a top choice for mobile applications, IoT devices, and smart wearables.
WLCSP Construction
Refer to the figure below for a representation of a typical WLCSP package with Redistribution Layer (RDL) and Under Bump Metallization (UBM) process. A WLCSP die has a first layer of organic dielectric (Polyimide 1), a metal redistribution layer (RDL) to re-route the signal path from the die peripheral I/O to a new desired location, and a second polyimide layer (Polyimide 2) to cover the RDL metal, which in turn is patterned into the solder ball array. To prevent diffusion and enable solder wetting, an under-bump metallization (UBM) layer is deposited on the RDL. The solder ball is a lead-free alloy. Backside wafer lamination, a protective polymer film, is optional for WLCSP productions. This polymer material offers both mechanical contact (i.e. SMT assembly pick and place) and UV light protection to the backside of the die surface.
WLCSP Manufacturing Process – From Wafer to Finished Product
The WLCSP manufacturing process is carried out directly on silicon wafers, helping to minimize production steps and significantly reduce costs. The entire process can be divided into three main stages: wafer preparation, wafer surface processing, and dicing – testing – final packaging.
The first step is wafer preparation, where silicon wafers are cleaned and surface-treated to ensure absolute purity. Next, the wafer undergoes Polyimide 1 (PI1) processing, followed by the Redistribution Layer (RDL) to redistribute electrical connection points, and finally Polyimide 2 (PI2) to protect and insulate the RDL layers. This is a critical stage in which ultra-thin metal layers are deposited to rearrange the signal paths between the chip and the printed circuit board (PCB). This process requires extremely high precision, as even a slight deviation can damage the entire wafer.
The next step is bump formation, where solder bumps are directly attached to the wafer surface. These bumps serve as both electrical and mechanical connections between the chip and the PCB. Once the bumps are formed, the wafer undergoes a reflow process (melting and bonding the bumps), followed by under bump metallization (UBM) – an intermediate metal layer that enhances adhesion and mechanical strength of the connections.
After surface processing is complete, the wafer is protected with an encapsulation or passivation layer to shield the chip from moisture, dust, and environmental impacts. This stage ensures the chip’s long-term reliability and durability during operation.
The wafer then undergoes electrical testing (Wafer Test) to verify proper functionality, after which it is protected and subjected to taping in preparation for back-side grinding (Turn over & Back Grinding). After de-taping, the wafer is laser marked and mounted onto a substrate (Mounting).
Once all wafer processing is complete, dicing is performed to separate individual chips using high-precision cutting equipment. Each chip is then inspected using AOI (Automated Optical Inspection) to detect surface defects or dimensional deviations. Next, the chips go through electrical testing to ensure they meet performance standards before shipment. Finally, the chips are packaged, labeled, and delivered to customers – becoming finished products ready for use in smartphones, IoT devices, and sensor systems.
________________________
Follow CT Semiconductor on Facebook for the latest updates and news!
